The disclosed embodiments of the present invention relate to data recovery at a receiver, and more particularly, to a transition enforcing coding (TEC) receiver for sampling vector signals without using clock and data recovery (CDR).
Transition enforcing coding (TEC) is a technique used to convert a bit sequence into a plurality of vector signals for transmission and reception between different chips. The TEC makes transition(s) always happen between adjacent states of the vector signals. For example, the vector signals records data bits representative of a current state during a current transmission clock cycle, and records data bits representative of a next state during a next transmission clock cycle, where the data bits representative of the current state and the data bits representative of the next state have at least one bit inversion (e.g., 1→0 or 0→1). The conventional TEC receiver generally has a clock and data recovery (CDR) circuit implemented therein. The CDR circuit is used to adjust the sampling timing for allowing a data sampler to get an optimal setup/hold time margin to sample the received vector signals correctly. However, the CDR circuit will lead to a larger chip area as well as higher power consumption, and will require an extra lock-in time for ensuring correct data sampling. Further, if the TEC transmitter needs to cover a wide range of data rates, the CDR circuit in the TEC receiver needs to be implemented using a wide-range CDR circuit, which results in a higher production cost.
Thus, there is a need for an innovative TEC receiver which is capable of correctly sampling the received vector signals without using any CDR circuit.